Eval-AD5570EB【PDF 17/24 页】True Accuracy, 16-Bit 12 V/15 V, Serial

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AD5570

Asynchronous LDAC:

In this mode, LDAC is high while data is

being clocked in. The DAC output is updated by taking LDAC

low any time after SYNC has been taken high. The update now

occurs on the falling edge of LDAC.

Rev. 0 | Page 17 of 24

Figure 36 shows a simplified block diagram of the input loading

circuitry.

OUT

DAC

INPUT SHIFT

OUTPUT

I/V AMPLIFIER

LDAC

SDO

SDIN

16-BIT

DAC

REFIN

SYNC

Figure 36. Simplified Serial Interface Showing Input Loading Circuitry

TRANSFER FUNCTION

Table 6 shows the ideal input code to output voltage relationship

for the AD5570.

Table 6. Binary Code Table

Digital Input

MSB

LSB

1111

1000

0000

0001

1000

0000

0111

1111

0000

Analog Output

OUT

+2 V

REF

× (32,767/32,768)

+2 V

REF

× (1/32,768)

0 V

2 V

REF

× (1/32,768)

2 V

REF

The output voltage expression is given by

]

65536

[

REFIN

OUT

where:

is the decimal equivalent of the code loaded to the DAC.

REFIN

is the reference voltage available at the REFIN pin.

CLEAR (CLR)

CLR is an active low digital input that allows the output to be

cleared to 0 V. When the CLR signal is brought back high, the

output stays at 0 V until LDAC is brought low. The relationship

between LDAC and CLR is explained further in Table 7.

Table 7. Relationships among PD, CLR, and LDAC

CLR

LDAC

Comments

PD has priority over LDAC and CLR. The

output remains at 0 V through an internal

20 k resistor. It is still possible to address

both the input register and DAC register

when the AD5570 is in power-down.

Data is written to the input register and

DAC register. CLR has higher priority over

LDAC; therefore, the output is at 0 V.

Data is written to the input register only.

The output is at 0 V and remains at 0 V,

when CLR is taken back high.

Data is written to the input register and

the DAC register. The output is driven to

the DAC level.

Data is written to the input register only.

The output of the DAC register is

unchanged.

POWER-DOWN (PD)

The power-down pin allows the user to place the AD5570 into a

power-down mode. When in this mode, power consumption is

at a minimum; the device consumes only 16 μA typically.

POWER-ON RESET

The AD5570 contains a power-on reset circuit that controls the

output during power-up and power-down. This is useful in

applications where the known state of the output of the DAC

during power-up is important. On power-up and power-down,

the output of the DAC, V

OUT

, is held at AGND.

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